ACTIVITY_STATE=Val_0x0
Slave Event Status Register
| SIR_EN | Slave Interrupt Request Enable In Slave mode of operation, this bit reflects whether the controller can initiate the SIR on the I3C bus or not. This bit is set or cleared by the I3C master through ENEC or DISEC CCC. |
| MR_EN | Master Request Enable In Slave mode of operation, this bit reflects whether the I3C can initiate the master request on the I3C bus or not. This bit is set or cleared by the I3C master through ENEC or DISEC CCC. |
| HJ_EN | Hot-Join Interrupt Enable This bit reflects whether the Hot-Join request interrupts are allowed on the I3C bus or not. The Slave can choose to disable Hot-Join capability of the slave I3C by setting this bit to 0x0 before enabling the I3C. When done so, the slave does not initiate Hot-Join and takes part in address assignment without initiating Hot-Join. If this field is not set to 0x0 by slave, it can be set or cleared by the I3C master through ENEC or DISEC CCC. Once disabled, CCC do not have any effect on this bit. |
| ACTIVITY_STATE | Activity State Status 0 (Val_0x0): ENTAS0 1 (Val_0x1): ENTAS1 2 (Val_0x2): ENTAS2 3 (Val_0x3): ENTAS3 |
| MRL_UPDATED | This bit indicates a SETMRL CCC is received by the slave. The updated MRL value can be read from I3C_SLV_MAX_LEN[MWL]. This status can be cleared by writing 0x1 to this bit after reading the updated MRL. |
| MWL_UPDATED | This bit indicates a SETMWL CCC is received by the slave. The updated MWL value can be read from I3C_SLV_MAX_LEN[MWL]. This status can be cleared by writing 0x1 to this bit after reading the updated MWL. |